1. Field of the Invention
The present invention relates to an SMTCMOS (Selective Multi Threshold Complementary Metal-oxide Semiconductor) having, for example, a plurality of threshold voltages.
2. Description of the Related Art
FIG. 7 shows a two-input NAND circuit 1. The NAND circuit 1 comprises P-channel MOS transistors (hereinafter referred to as “PMOS transistors”) P1 and P2, and N-channel MOS transistors (hereinafter referred to as “NMOS transistors”) N1 and N2. The threshold voltage of the PMOS transistors P1 and P2 is set to, for example, −0.55 V, while that of the NMOS transistors N1 and N2 is set to, for example, 0.55 V. First and second power supply voltages Vdd1 and Vss1 are set to, for example, 1.2 V and 0 V, respectively. The high and low levels of an input signal A supplied to the gates of the transistors P1 and N1 are set to 1.2 V and 0 V, respectively. Similarly, the high and low levels of an input signal B supplied to the gates of the transistors P2 and N2 are set to 1.2 V and 0 V, respectively.
FIG. 8 illustrates a two-input NAND circuit example 11 utilizing an SMTCMOS. The NAND circuit 11 comprises PMOS transistors P11 and P12 and NMOS transistors N11 and N12. The threshold voltage of the PMOS transistors P11 and P12 is set to, for example, −0.35 V, while that of the NMOS transistors N11 and N12 is set to, for example, 0.35 V. The first and second power supply voltages Vdd1 and Vss1 are set to, for example, 1.2 V and 0 V, is respectively.
The source of the NMOS transistor N12 is connected to the drain of an NMOS transistor N13. The source of the NMOS transistor N13 is supplied with the second power supply voltage Vss1 (0 V). The threshold voltage of the NMOS transistor N13 is set to, for example, 0.55 V. The NMOS transistor N13 performs switching to supply a power supply voltage to the NAND circuit 11 or to stop the supply of the power supply voltage. The NMOS transistor N13 is controlled by a control signal Sc so that it is ON during the operation of the NAND circuit 11, and OFF during the non-operation (standby state) of the circuit 11.
A PMOS transistor P13 is connected in parallel to the PMOS transistor P12. The PMOS transistor P13 is controlled by the control signal Sc so that it is ON during the non-operation of the NAND circuit 11, thereby setting the output terminal OUT of the NAND circuit 11 to a high level regardless of an input signal. The threshold voltage of the PMOS transistor P13 is set to, for example, −0.55 V or −0.35 V. The high and low levels of the input signal A supplied to the gates of the transistors P11 and N11 are set to 1.2 V and 0 V, respectively. Similarly, the high and low levels of the input signal B supplied to the gates of the transistors P12 and N12 are set to 1.2 V and 0 V, respectively. Further, the high and low levels of the control signal Sc supplied to the gates of the transistors N13 and P13 are also set to 1.2 V and 0 V, respectively.
In logic circuits of this type, the total ON resistance is determined according to the required operation speed. In the NAND circuit 1 shown in FIG. 7 and NAND circuit 11 shown in FIG. 8, the required ON resistance is, for example, 1.2 kΩ or less. The ON resistance of this type of NAND circuit is determined from the resistances of the NMOS transistors incorporated therein. In the NAND circuit 1 of FIG. 7, when the first power supply voltage Vdd1 is 1.2 V, the ON resistance of each of the NMOS transistors N1 and N2 is set to approx. 600 Ω. Accordingly, the total ON resistance of the NMOS transistors N1 and N2 is 1.2 kΩ, which meets the specification.
In the NAND circuit 11 of FIG. 8, when the first power supply voltage Vdd1 is 1.2 V, the ON resistance of each of the NMOS transistors N11 and N12 is set to approx. 100 Ω. Further, the ON resistance of the NMOS transistor N13 is set to approx. 600 Ω. Accordingly, the total ON resistance is 800 Ω, which satisfies the specification concerning the maximum total ON resistance (1.2 kΩ). Thus, any specification can be satisfied by appropriately setting the ON resistance of each transistor.
However, in recent semiconductor integrated circuits for use in, for example, cellular phones, there is a demand for further reducing the power supply voltage, to save power. Power consumption Pc is given by the following equation:Pc=f·C·V2where f represents frequency, C parasitic capacitance, and V power supply voltage.
To save power, for example, the first power supply voltage Vdd1 and the high level of an input signal may be reduced from 1.2 V to 1.0 V. In the circuit shown in FIG. 7, it is necessary to reduce the leak current in the non-operation period, therefore the threshold voltage of each transistor is set high. In this case, if the power supply voltage and signal voltage are reduced as described above, without changing the threshold voltage of each transistor, the ON resistance of each of the NMOS transistors N1 and N2 is increased from 600 Ω to 1.2 kΩ, thereby increasing the total ON resistance from 1.2 kΩ to 2.4 kΩ. Thus, it is almost impossible to satisfy the specification concerning the maximum total ON resistance. Moreover, an increase in the total ON resistance makes it difficult for the circuit to perform high-speed operations. In order to avoid this, if the threshold voltage of each transistor is reduced to reduce the total ON resistance, the leak current inevitably increases. In light of this, it is not advisable to reduce the threshold voltage. Thus, it is difficult to achieve voltage reduction in the circuit of FIG. 7.
On the other hand, in the circuit shown in FIG. 8, the threshold voltage of each transistor incorporated in the NAND circuit 11 is set low. Therefore, if the power supply voltage and signal voltage are reduced from 1.2 V to 1.0 V, the ON resistance of each of the NMOS transistors N11 and N12 becomes approx. 200 Ω. This ON resistance does not significantly influence high-speed operations. However, the threshold voltage of the NMOS transistor N13 for supply of a power voltage is set higher than that of the transistors incorporated in the NAND circuit 11. Therefore, if the power supply voltage and signal voltage are reduced to 1.0 V, the ON resistance of the NMOS transistor N13 becomes 1.2 kΩ. As a result, the total ON resistance becomes 1.6 kΩ, which makes it very difficult to satisfy the specification concerning the maximum total ON resistance of 1.2 kΩ. Moreover, an increase in the total ON resistance makes it difficult for the circuit to perform high-speed operations. In light of the above, there is a demand for the development of a semiconductor integrated circuit that incorporates a logic circuit section drivable by a low voltage, and can operate at a high speed.